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ds97tad0300 p r e l i m i n a r y 1-1 1 p reliminary p roduct s pecification Z89135/z89136 1 l ow -c ost dtad c ontroller features n 24 kb of z8 program rom (Z89135) n watch-dog timer and power-on reset n low power stop mode n on-chip oscillator which accepts a crystal or external clock drive n two 8-bit z8 counter timers with 6-bit prescaler n global power-down mode n low power consumption - 200 mw (typical) n two comparators with programmable interrupt priority n six vectored, priority z8 interrupts n ram and rom protect n clock speed of 20.48 mhz n 16-bit digital signal processor (dsp) n 6k word dsp program rom n 512 words on-chip dsp ram n 8-bit a/d converter with up to 128 khz sample rate n 10-bit pwm d/a converter (4 khz to 64 khz) n three vectored, prioritized dsp interrupts n two dsp timers to support different a/d and n d/a sampling rates n z8 and dsp operation in parallel n ibm pc-based development tools n developer? toolbox for t.a.m. applications ibm is a registered trademark of international business machines corp. general description the Z89135/136 is a fully integrated, dual processor con- troller designed for low-cost digital telephone answering machines. the i/o control processor is a z8 mcu with 24 kb of program memory, two 8-bit counter/timers, and up to 47 i/o pins. the dsp is a 16-bit processor with a 24-bit alu and accumulator, 512 x 16 bits of ram, single cycle instructions, and 6k word program rom plus constants memory. the chip also contains a half-flash 8-bit a/d con- verter with up to 128 khz sample rate and 10-bit pwm d/a converter. the sampling rates for the converters are pro- grammable. the precision of the 8-bit a/d may be extend- ed by resampling the data at a lower rate in software. the z8 and dsp processors are coupled by mailbox regis- ters and an interrupt system, which allows dsp or z8 pro- grams to be directed by events in each other? domain. the z89136 is the romless version of the Z89135. the dsp is not romless. the dsp's program memory is al- ways the internal rom. device rom (kb) ram* (bytes) i/o lines speed (mhz) Z89135 24 256 47 20 z89136 24 256 47 20
Z89135/136 (romless) low-cost dtad controller zilog 1-2 p r e l i m i n a r y ds97tad0300 general description (continued) figure 1. functional block diagram port 0 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 p31 p32 p33 p40 p41 p42 p43 p44 p45 p46 p47 p50 p51 p52 p53 p54 p55 p56 p57 rmls /as /ds r/w timer 0 capture reg. port 3 port 1 port 4 port 2 port 5 timer 1 register file 256 x 8 bit 24 kbytes program rom (z89165) z8 core register bus internal address bus internal data bus expanded register file (z8) peripheral register (dsp) expanded register bus extended bus of the dsp 6k words program rom dsp core internal address bus internal data bus dsp port pwm (10-bit) adc (8-bit) timer 2 timer 3 extended bus of the dsp ext. memory control osc power xtal1 xtal2 vdd gnd /reset int 1 int 2 dsp0 dsp1 an in an vdd an gnd vref+ vref- pwm 256 word ram 0 256 word ram 1 p34 p35 p36 p37 input output i/o (bit programmable) i/o (bit programmable) address or i/o (nibble programmable) address/data or i/o (byte programmable) i/o (bit programmable) mailbox
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-3 1 z8 core processor the z8 is zilog? 8-bit mcu core with an expanded regis- ter file to allow access to register-mapped peripheral and i/o circuits. the z8 mcu offers a flexible i/o scheme, an efficient register and address space structure, and a num- ber of ancillary features. for applications demanding powerful i/o capabilities, the Z89135/136 offers 47 pins dedicated to input and output. these lines are grouped into six ports. each port is config- urable under software control to provide timing, status sig- nals and parallel i/o with or without handshake. there are four basic memory resources for the z8 that are available to support a wide range of configurations: pro- gram memory, register file, data memory, and expanded register file. the z8 core processor is characterized by an efficient register file that allows any of 256 on-board data and control registers to be the source and/or the des- tination of almost any instruction. traditional microproces- sor accumulator bottlenecks are eliminated. the register file is composed of 236 bytes of general-pur- pose registers, four i/o port register,s and 15 control and status registers. the expanded register file consists of mailbox registers, wdt mode register, dsp control regis- ter, stop-mode recovery register, port configuration reg- ister, and the control and data registers for port 4 and port 5. to unburden the software from supporting the real-time problems, such as counting/timing and data communica- tion, the z8 offers two on-chip counter/timers with a large number of user selectable modes. watch-dog timer and stop-mode recovery features are software driven by setting specific bits in control registers. stop and halt instructions support reduced power op- eration. the low power stop mode allows parameter in- formation to be stored in the register file if power fails. an external capacitor or battery retains power to the device. dsp coprocessor the dsp coprocessor is a second generation, 16-bit two? complement cmos digital signal processor (dsp). most instructions, including multiply and accumulate, are ac- complished in a single clock cycle. the processor contains two on-chip data ram blocks of 256 words, a 6k word pro- gram rom, 24-bit alu, 16 x 16 multiplier, 24-bit accumu- lator, shifter, six-level stack, three vectored interrupts, and two inputs for conditional program jumps. each ram block contains a set of four pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. the data rams can be simul- taneously addressed and loaded to the multiplier for a true single cycle scalar multiply. four external dsp registers are mapped into the expand- ed register file of the z8. communication between the z8 and the dsp occurs through those common registers which form the mailbox registers. the analog signal is generated by a 10-bit resolution pulse width modulator. the pwm output is a digital signal with cmos output levels. the output signal has a resolution of 1 in 1024 with a sampling rate of 16 khz (xtal = 20.48 mhz). the sampling rate can be changed under software control and can be set at 4, 10, 16, and 64 khz. the dy- namic range of the pwm is from 0 to 4v. an 8-bit resolution half-flash a/d converter is provided. the conversion is conducted with a sampling frequency of 8, 16, 32, 64, or 128 khz. (xtal = 20.48 mhz) in order to provide oversampling. the input signal is 4v peak to peak. scaling is normally 1.25v for the 2.5v peak to peak off- set. two additional timers (timer2 and timer3) have been added to support different sampling rates for the a/d and d/a converters. these timers are free running counters that divide the crystal frequency to the appropriate sam- pling of frequency. notes: all signals with a preceding front slash, "/", are ac- tive low. for example, b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss
Z89135/136 (romless) low-cost dtad controller zilog 1-4 p r e l i m i n a r y ds97tad0300 figure 2. Z89135 68-pin plcc pin assignments Z89135 7 8 9 654321 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p31 p32 p33 p34 vdd p35 p14 dsp1 dsp0 p36 p13 p37 p40 p12 p06 p41 p42 vref+ anin vref- angnd /as /reset r//w pwm p10 p47 p11 p46 p53 p45 p44 p43 n/c xtal2 xtal1 p22 p56 p23 p55 p54 gnd p17 p05 p24 p16 p25 p15 p26 p27 n/c p00 p01 p02 p03 p57 p50 p04 vdd rmls /ds p51 p52 p21 p20 p07 gnd anvdd
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-5 1 table 1. Z89135 68-pin plastic leaded chip carrier, pin identi?ation pin # symbol function direction 1 rmls romless control input 2v dd power supply 3 p04 port 0, bit 4 input/output 4 p50 port 5, bit 0 input/output 5 p57 port 5, bit 7 input/output 6 p03 port 0, bit 3 input/output 7 p02 port 0, bit 2 input/output 8 p01 port 0, bit 1 input/output 9 p00 port 0, bit 0 input/output 10 xtal2 crystal oscillator clock output 11 xtal1 crystal oscillator clock input 12 p22 port 2, bit 2 input/output 13 p56 port 5, bit 6 input/output 14 p23 port 2, bit 3 input/output 15 p55 port 5, bit 5 input/output 16 p54 port 5, bit 4 input/output 17 gnd ground 18 p17 port 1, bit 7 input/output 19 p05 port 0, bit 5 input/output 20 p24 port 2, bit 4 input/output 21 p16 port 1, bit 6 input/output 22 p25 port 2, bit 5 input/output 23 p15 port 1, bit 5 input/output 24 p26 port 2, bit 6 input/output 25 p27 port 2, bit 7 input/output 26 n/c not connected 27 p31 port 3, bit 1 input 28 p32 port 3, bit 2 input 29 p33 port 3, bit 3 input 30 p34 port 3, bit 4 output 31 v dd power supply 32 p35 port 3, bit 5 output 33 p14 port 1, bit 4 input/output 34 dsp1 dsp user output 1 output 35 dsp0 dsp user output 0 output 36 p36 port 3, bit 7 output 37 p13 port 1, bit 3 input/output 38 p37 port 3, bit 7 output 39 p40 port 4, bit 0 input/output 40 p12 port 1, bit 2 input/output 41 p06 port 0, bit 6 input/output 42 p41 port 4, bit 1 input/output 43 p42 port 4, bit 2 input/output 44 n/c not connected 45 p43 port 4, bit 3 input/output 46 p44 port 4, bit 4 input/output 47 p45 port 4, bit 5 input/output 48 p53 port 5, bit 3 input/output 49 p46 port 4, bit 6 input/output 50 p11 port 1, bit 1 input/output 51 p47 port 4, bit 7 input/output 52 p10 port 1, bit 0 input/output 53 pwm pulse width modulator output 54 r//w read/write output 55 /reset reset input/output 56 /as address strobe output 57 angnd analog ground 58 v ref- analog voltage ref. input 59 an in analog input input 60 v ref+ analog voltage ref. input 61 anv dd analog power supply 62 gnd ground 63 p07 port 0, bit 7 input/output 64 p20 port 2, bit 0 input/output 65 p21 port 2, bit 1 input/output 66 p52 port 5, bit 2 input/output 67 p51 port 5, bit 1 input/output 68 /ds data strobe output table 1. Z89135 68-pin plastic leaded chip carrier, pin identi?ation pin # symbol function direction
Z89135/136 (romless) low-cost dtad controller zilog 1-6 p r e l i m i n a r y ds97tad0300 figure 3. z89136 68-pin plcc pin assignments z89136 7 8 9 654321 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p31 p32 p33 p34 vdd p35 p14 dsp1 dsp0 p36 p13 p37 p40 p12 p06 p41 p42 vref+ anin vref- angnd /as /reset r//w pwm p10 p47 p11 p46 p53 p45 p44 p43 /sync xtal2 xtal1 p22 p56 p23 p55 p54 gnd p17 p05 p24 p16 p25 p15 p26 p27 sclk p00 p01 p02 p03 p57 p50 p04 vdd vdd /ds p51 p52 p21 p20 p07 gnd anvdd
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-7 1 table 2. z89136 68-pin plastic leaded chip carrier, pin identi?ation pin # symbol function direction 1v dd power supply 2v dd power supply 3 p04 port 0, bit 4 input/output 4 p50 port 5, bit 0 input/output 5 p57 port 5, bit 7 input/output 6 p03 port 0, bit 3 input/output 7 p02 port 0, bit 2 input/output 8 p01 port 0, bit 1 input/output 9 p00 port 0, bit 0 input/output 10 xtal2 crystal oscillator clock output 11 xtal1 crystal oscillator clock input 12 p22 port 2, bit 2 input/output 13 p56 port 5, bit 6 input/output 14 p23 port 2, bit 3 input/output 15 p55 port 5, bit 5 input/output 16 p54 port 5, bit 4 input/output 17 gnd ground 18 p17 port 1, bit 7 input/output 19 p05 port 0, bit 5 input/output 20 p24 port 2, bit 4 input/output 21 p16 port 1, bit 6 input/output 22 p25 port 2, bit 5 input/output 23 p15 port 1, bit 5 input/output 24 p26 port 2, bit 6 input/output 25 p27 port 2, bit 7 input/output 26 sclk system clock output 27 p31 port 3, bit 1 input 28 p32 port 3, bit 2 input 29 p33 port 3, bit 3 input 30 p34 port 3, bit 4 output 31 v dd power supply 32 p35 port 3, bit 5 output 33 p14 port 1, bit 4 input/output 34 dsp1 dsp user output 1 output 35 dsp0 dsp user output 0 output 36 p36 port 3, bit 7 output 37 p13 port 1, bit 3 input/output 38 p37 port 3, bit 7 output 39 p40 port 4, bit 0 input/output 40 p12 port 1, bit 2 input/output 41 p06 port 0, bit 6 input/output 42 p41 port 4, bit 1 input/output 43 p42 port 4, bit 2 input/output 44 /sync synchronization pin output 45 p43 port 4, bit 3 input/output 46 p44 port 4, bit 4 input/output 47 p45 port 4, bit 5 input/output 48 p53 port 5, bit 3 input/output 49 p46 port 4, bit 6 input/output 50 p11 port 1, bit 1 input/output 51 p47 port 4, bit 7 input/output 52 p10 port 1, bit 0 input/output 53 pwm pulse width modulator output 54 r//w read/write output 55 /reset reset input/output 56 /as address strobe output 57 angnd analog ground 58 v ref- analog voltage ref. input 59 an in analog input input 60 v ref+ analog voltage ref. input 61 anv dd analog power supply 62 gnd ground 63 p07 port 0, bit 7 input/output 64 p20 port 2, bit 0 input/output 65 p21 port 2, bit 1 input/output 66 p52 port 5, bit 2 input/output 67 p51 port 5, bit 1 input/output 68 /ds data strobe output table 2. z89136 68-pin plastic leaded chip carrier, pin identi?ation pin # symbol function direction
Z89135/136 (romless) low-cost dtad controller zilog 1-8 p r e l i m i n a r y ds97tad0300 a/d converter (adc) figure 4 shows the input circuit of the adc. when conver- sion starts, the analog input voltage from the input is con- nected to the msb and lsb flash converter inputs as shown in the input impedance ckt diagram. shunting 31 parallel internal resistances of the analog switches and si- multaneously charging 31 parallel 1 pf capacitors is equiv- alent to a 400 ohms input impedance in parallel with a 31 pf capacitor. other input stray capacitance adds about 10 pf to the input load. input source resistances up to 2 ko- hms can be used under normal operating conditions with- out any degradation of the input settling time. for larger in- put source resistance, longer conversion cycle times may be required to compensate the input settling time problem. v ref is set using the v ref + pin. absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. exposure to ab- solute maximum rating conditions for an extended period may affect device reliability. figure 4. input impedance of adc cmos switch on resistance 2 - 5 k w c parasitic r source v ref c .5 pf v ref c .5 pf v ref c .5 pf 31 cmos digital comparators symbol description min max units v cc supply voltage (*) ?.3 +7.0 v t stg storage temp ?5 +150 c t a oper ambient temp ? c notes: voltage on all pins with respect to gnd. ? see ordering information.
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-9 1 standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 5). capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. dc electrical characteristics figure 5. test load diagram +5v from output under test 150 pf 9.1 k w 2.1 k w parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf t a = 0 c to +55 c typical sym parameter v cc min max @ 25 c units i cc supply current 5.0v 65 40 ma i cc1 halt mode current 5.0v 20 6 ma i cc2 stop mode current 5.0v 400 300 m a note: 5.0v 0.25v.
Z89135/136 (romless) low-cost dtad controller zilog 1-10 p r e l i m i n a r y ds97tad0300 dc electrical characteristics t a = 0 c to +55 c typical sym parameter v cc min max @ 25 c units conditions v max max input voltage 5.0v 7 v ch clock input high voltage 5.0v 0.9 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 5.0v gnd?.3 0.1 v cc 1.5 v driven by external clock generator v ih input high voltage 5.0v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 5.0v gnd?.3 0.2 v cc 1.5 v v oh output high voltage 5.0v v cc ?.4 4.8 v i oh = ?.0 ma v ol1 output low voltage 5.0v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 5.0v 1.2 0.3 v i ol = +12 ma, 3 pin max v rh reset input high voltage 5.0v 0.8 v cc v cc 2.1 v v rl reset input low voltage 5.0v gnd?.3 0.2 v cc 1.7 v offset comparator input offset 5.0v 25 10 mv voltage i il input leakage 5.0v ? 5 25 m av in = ov, v cc i ol output leakage 5.0v ? 5 25 m av in = ov, v cc i ir reset input current 5.0v ?5 ?0 m a note: 5.0v 0.25v
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-11 1 dc electrical characteristics z89165 a/d converter t a = 0 c to +55 c sym parameter v dd min max units conditions i il input leakage analog input 5.0v 40 m a anv dd v in v refh v refl = = = = 5.50 0.00 5.50 0.00 v v v v i ih input leakage analog input 5.25v 2.00 m a anv dd v in v refh v refl = = = = 5.50 5.50 5.50 0.00 v v v v i vrefh input current 5.25v 2.00 ma v in v refl anv dd = = = 5.50 0.00 5.50 v v v i v refl input current 5.25v 80 m a vin v refl anv dd = = = 5.50 5.50 5.50 v v v ivefl input current 5.25v -2.00 ma v in v refh anv dd = = = 0.00 5.50 0.00 v v v i vrefl input current 5.25v -80 m av in v refh anv dd = = = 0.00 5.50 5.50 v v v
Z89135/136 (romless) low-cost dtad controller zilog 1-12 p r e l i m i n a r y ds97tad0300 dc electrical characteristics 21 other non-regular i/o t a = 0 c to +55 c sym parameter v dd min max units conditions i irh input current romless pin 5.25v 6.00 m av in = 5.25 v i ir1 input current romless pin 5.25v 6.00 m av in = 0.00 v i ir input current romless pin during reset active 5.25v 1.00 ma v in = 5.25 v i ihx2 input current xtal2 pin in stop mode 5.25v 1.00 m av in = 0.00 v i ilx2 input current xtal2 pin in stop mode 5.25v 1.00 m av in = 5.25 v i ihx1 input current xtal1 pin 5.25v 30 m av in = 0.00 v i ilx1 input current xtal1 pin 5.25v 30 m av in = 5.25 v v olxr output low voltage xtal2 reset inactive 5.25v 1.20 v i ol = 4.00 ma v olx output low voltage xtal2 reset inactive 5.25v 0.60 v i ol = 1.00 ma v ohxr output high voltage xtal2 reset inactive 5.25v 4.00 v i oh = 4.00 ma iv ohx output high voltage xtal2 reset inactive 5.25v 4.00 v i oh =1.00 ma i ih input current p31,p32,p33 5.25v 1.00 m av in = 5.25 v i il input current p31, p32, p33 5.25v 1.00 m av in = 0.00 v
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-13 1 ac characteristic external i/o or memory read and write timing diagram figure 6. external i/o or memory read/write timing r//w 9 12 19 3 16 13 4 5 8 18 11 6 17 10 15 7 14 2 1 port 0, /dm port 1 /as /ds (read) port1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0
Z89135/136 (romless) low-cost dtad controller zilog 1-14 p r e l i m i n a r y ds97tad0300 ac characteristics external i/o or memory read and write timing table t a =0 c to +55 c no symbol parameter v cc min max units notes 1 tda(as) address valid to /as rise delay 5.0v 25 ns 2,3 2 tdas(a) /as rise to address float delay 5.0v 35 ns 2,3 3 tdas(dr) /as rise to read data reqd valid 5.0v 150 ns 1,2,3 4 twas /as low width 5.0v 35 ns 2,3 5 tdaz(ds) address float to /ds fall 5.0v 0 ns 6 twdsr /ds (read) low width 5.0v 125 ns 1,2,3 7 twdsw /ds (write) low width 5.0v 75 ns 1,2,3 8 tddsr(dr) /ds fall to read data reqd valid 5.0v 90 ns 1,2,3 9 thdr(ds) read data to /ds rise hold time 5.0v 0 ns 2,3 10 tdds(a) /ds rise to address active delay 5.0v 40 ns 2,3 11 tdds(as) /ds rise to /as fall delay 5.0v 35 ns 2,3 12 tdr/w(as) r//w valid to /as rise delay 5.0v 25 ns 2,3 13 tdds(r/w) /ds rise to r//w not valid 5.0v 35 ns 2,3 14 tddw(dsw) write data valid to /ds fall (write) delay 5.0v 40 ns 2,3 15 tdds(dw) /ds rise to write data not valid delay 5.0v 25 ns 2,3 16 tda(dr) address valid to read data reqd valid 5.0v 180 ns 1,2,3 17 tdas(ds) /as rise to /ds fall delay 5.0v 48 ns 2,3 18 tddi(ds) data input setup to /ds rise 5.0v 50 ns 1,2,3 19 tddm(as) /dm valid to /as fall delay 5.0v 20 ns 2,3 notes: 1. when using extended memory timing, add 2 tpc. 2. timing numbers given are for minimum tpc. 3. see clock cycle dependent characteristics table. 5.0v 0.25v standard test load all timing references use 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0.
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-15 1 ac electrical characteristics additional timing diagram figure 7. additional timing clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 11 clock setup 10 9 stop mode recovery source
Z89135/136 (romless) low-cost dtad controller zilog 1-16 p r e l i m i n a r y ds97tad0300 ac electrical characteristics additional timing table t a =0 c to +55 c no symbol parameter v cc min max units notes 1 tpc input clock period 5.0v 48.83 ns 1 2 trc,tfc clock input rise & fall times 5.0v 6 ns 1 3 twc input clock width 5.0v 17 ns 1 4 twtinl timer input low width 5.0v 70 ns 5 twtinh timer input high width 5.0v 3tpc 1 6 tptin timer input period 5.0v 8tpc 1 7 trtin, tftin timer input rise & fall timer 5.0v 100 ns 1 8a twil int. request low time 5.0v 70 ns 1,2 8b twil int. request low time 5.0v 3tpc 1 9 twih int. request input high time 5.0v 3tpc 1 10 twsm stop-mode recovery width spec 5.0v 12 5tpc ns 1 11 tost oscillator start-up time 5.0v 5tpc 3 12 twdt watch-dog timer 5.0v 5.0v 5.0v 5.0v 5 15 25 100 ms ms ms ms d1 = 0, d0 = 0 [4] d1 = 0, d0 = 1 [4] d1 = 1, d0 = 0 [4] d1 = 1, d0 = 1 [4] notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31) 3. smr-d5 = 0 4. reg. wdt 5.0v 0.25v
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-17 1 ac electrical characteristics handshake timing diagrams figure 8. input handshake timing data in 1 3 4 /dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid 5 6 2 figure 9. output handshake timing data out /dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
Z89135/136 (romless) low-cost dtad controller zilog 1-18 p r e l i m i n a r y ds97tad0300 ac electrical characteristics (continued) handshake timing table v cc t a = 0 c to +55 c min max data direction no symbol parameter units 1 tsdi(dav) data in setup time 5.0v 0 ns in 2 thdi(dav) rdy to data hold time 5.0v 0 ns in 3 twdav data available width 5.0v 40 ns in 4 tddavi(rdy) dav fall to rdy fall delay 5.0v 70 ns in 5 tddavid(rdy) dav rise to rdy rise delay 5.0v 40 ns in 6 tddo(dav) rdy rise to dav fall delay 5.0v 0 ns in 7 tcldav0(rdy) data out to dav fall delay 5.0v tpc ns out 8 tcldav0(rdy) dav fall to rdy fall delay 5.0v 0 ns out 9 tdrdy0(dav) rdy fall to dav rise delay 5.0v 70 ns out 10 twrdy rdy width 5.0v 40 ns out 11 tdrdy0d(dav) rdy rise to dav fall delay 5.0v 40 ns out note: 5.0v 0.25v
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-19 1 ac electrical characteristics a/d electrical characteristics t a = 0 c ?5 c; v cc = 5.0v 0.25v parameter min max typical units resolution 8 bits integral non-linearity 1 0.5 lsb differential non-linearity 0.5 lsb zero error at 25 c50mv power dissipation 75 35 mw clock frequency 20.48 mhz clock pulse width 35 ns analog input voltage range an gnd anv cc v conversion time 2 m s input capacitance on 60 pf va hi range damage an gnd anv cc v va lo range damage an gnd anv cc v an gnd v ss anv cc v anv cc an gnd v cc v
Z89135/136 (romless) low-cost dtad controller zilog 1-20 p r e l i m i n a r y ds97tad0300 pin fuctions /reset. (input/output, active low). this pin initializes the mcu. reset is accomplished either through power-on re- set (por), watch-dog timer reset, stop-mode recovery, or external reset. during por and wdt reset, the inter- nally generated reset is driving the reset pin low for the por time. any devices driving the reset line must be open drain to avoid damage from a possible conflict during reset conditions. a /reset will reset both the z8 and the dsp. for the z8: after the por time, /reset is a schmitt-triggered input. to avoid asynchronous and noisy reset problems, the z8 is equipped with a reset filter of four external clocks (4tpc). if the external reset signal is less than 4tpc in du- ration, no reset occurs. on the fifth clock after the reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the du- ration of the external reset, whichever is longer. program execution begins at location 000ch (hexadecimal), 5-10 tpc cycles after the /reset is released. the z8 does not reset wdt, smr, p2m, and p3m registers on a stop- mode recovery operation. for the dsp: a low level on the /reset pin generates an internal reset signal. the /reset signal must be kept low for at least one clock cycle. the cpu will fetch a new program counter (pc) value from program memory address 0ffch after the reset signal is released. rmls. romless (input, active high). this pin, when con- nected to vdd, disables the internal z8 rom. (note that, when pulled low to gnd that part functions normally as the rom version). the dsp can not be configured as romless. this pin is only available on the Z89135. r//w. read/write (output, write low). the r//w signal de- fines the signal flow when the z8 is reading or writing to ex- ternal program or data memory. the z8 is reading when this pin is high and writing when this pin is low. /as. address strobe (output, active low). address strobe is pulsed once at the beginning of each machine cycle. ad- dress output is through port 0/port 1 for all external pro- grams. memory address transfers are valid at the trailing edge of /as. under program control, /as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. /ds. data strobe (output, active low). data strobe is acti- vated once for each external memory transfer. for read operations, data must be available prior to the trailing edge of /ds. for write operations, the falling edge of /ds indi- cates that output data is valid. xtal1. crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc, rc net- work or an external single-phase clock to the on-chip oscil- lator input. xtal2. crystal 2 (time-based output). this pin connects a parallel-resonant, crystal, ceramic resonant, or lc network to the on-chip oscillator output. dsp0. (output). dsp0 is a general-purpose output pin connected to bit 6 of the analog control register (dsp ext4). this bit has no special significance and may be used to output data by writing to bit 6 of the acr. dsp1. (output). dsp1 is a general-purpose output pin connected to bit 7 of the analog control register (dsp ext4). this bit has no special significance and may be used to output data by writing to bit 7 of the acr. sclk. system clock (output). sclk outputs the system clock. this pin is available on the z89136. /sync. synchronize (output). this signal indicates the last clock cycle of the current executing z8 instruction. this pin is only available on the z89136. pwm. pulse width modulator (output). the pwm is a 10- bit resolution d/a converter. this output is a digital signal with cmos output levels. an in . (input). analog input for the a/d converter. anv dd . analog power supply for the a/d converter. an gnd . analog ground for the a/d converter. v ref+ . (input). reference voltage (high) for the a/d con- verter. v ref . (input). reference voltage (low) for the a/d convert- er. v dd . digital power supply for the Z89135. gnd. digital ground for the Z89135.
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-21 1 port 0. (p07-p00). port 0 is an 8-bit, bidirectional, cmos- compatible port. these eight i/o lines are configured un- der software control as a nibble i/o port, or as an address port for interfacing external memory. the input buffers are schmitt-triggered and the output drivers are push-pull. port 0 is placed under handshake control. in this configu- ration, port 3, lines p32 and p35 are used as the hand- shake control /dav0 and rdy0. handshake signal direc- tion is dictated by the i/o direction to port 0 of the upper nibble p07-p04. the lower nibble must have the same di- rection as the upper nibble. the auto latch on port 0 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces excessive supply cur- rent flow in the input buffer. for external memory references, port 0 provides address bits a11-a8 (lower nibble) or a15-a8 (lower and upper nib- ble) depending on the required address space. if the ad- dress range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for addressing. if one or both nibbles are needed for i/o operation, they are configured by writ- ing to the port 0 mode register. in romless mode, after a hardware reset, port 0 is config- ured as address lines a15-a8, and extended timing is set to accommodate slow memory access. the initialization routine can include reconfiguration to eliminate this ex- tended timing mode. (in rom mode, port 0 is defined as input after reset.) port 0 is set in the high-impedance mode if selected as an address output state along with port 1 and the control sig- nals /as, /ds and r//w (figure 10). figure 10. port 0 con?uration oen out in pa d auto latch port 0 (i/o or a15 - a8) handshake controls /dav0 and rdy0 (p32 and p35) Z89135/136 mcu 4 4 r = 500 k w 1.5 2.3v hysteresis
Z89135/136 (romless) low-cost dtad controller zilog 1-22 p r e l i m i n a r y ds97tad0300 pin fuctions (continued) port 1. (p17-p10). port 1 is an 8-bit, bidirectional, cmos- compatible port (figure11). it has multiplexed address (a7-a0) and data (d7-d0) ports. these eight i/o lines are programmed as inputs or outputs, or can be configured un- der software control as an address/data port for interfac- ing external memory. the input buffers are schmitt trig- gered and the output drivers are push-pull. port 1 may be placed under handshake control. in this con- figuration, port 3, lines p33 and p34 are used as the hand- shake controls rdy1 and /dav1 (ready and data avail- able). memory locations greater than 24575 (in rom mode) are referenced through port 1. to interface external memory, port 1 must be programmed for the multiplexed address/data mode. if more than 256 external locations are required, port 0 outputs the additional lines. port 1 can be placed in the high-impedance state along with port 0, /as, /ds and r//w, allowing the Z89135/136 to share common resources in multiprocessor and dma applications. figure 11. port 1 con?uration oen out in pa d auto latch handshake controls /dav2 and rdy2 (p31 and p36) Z89135/136 mcu r = 500 k w 1.5 2.3v hysteresis port 1 (i/o or ad7 - ad0) 8
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-23 1 port 2. (p27-p20). port 2 is an 8-bit, bidirectional, cmos- compatible i/o port. these eight i/o lines are configured under software control as an input or output, independent- ly. port 2 is always available for i/o operation. the input buffers are schmitt triggered. bits programmed as outputs may be globally programmed as either push-pull or open- drain. port 2 may be placed under handshake control. in this con- figuration, port 3 lines p31 and p36 are used as the hand- shake controls lines /dav2 and rdy2. the handshake signal assignment for port 3 lines p31 and p36 is dictated by the direction (input or output) assigned to bit 7, port 2 (figure 12). the auto latch on port 2 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces excessive supply cur- rent flow in the input buffer. figure 12. port 2 con?uration oen out in pa d auto latch port 2 (i/o) handshake controls /dav2 and rdy2 (p31 and p36) Z89135/136 mcu r = 500 k w 1.5 2.3v hysteresis open drain
Z89135/136 (romless) low-cost dtad controller zilog 1-24 p r e l i m i n a r y ds97tad0300 pin fuctions (continued) port 3. (p37-p31). port 3 is a 7-bit, cmos-compatible port with three fixed inputs (p33-p31) and four fixed outputs (p37-p34). it is configured under software control for in- put/output, counter/timers, interrupt, and port handshakes. pins p31, p32, and p33 are standard cmos inputs; out- puts are push-pull. two on-board comparators can process analog signals on p31 and p32 with reference to the voltage on p33. the an- alog function is enabled by programming the port 3 mode register (bit 1). port 3, pin 3 is a falling edge interrupt in- put. p31 and p32 are programmable as rising, falling or both edge-triggered interrupts (irq register bits 6 and 7). p33 is the comparator reference voltage input. access to counter/timers 1 is through p31 (t in ) and p36 (t out ). handshake lines for ports 0, 1, and 2 are available on p31 through p36. port 3 also provides the following control functions: hand- shake for ports 0, 1, and 2 (/dav and rdy); three external interrupt request signals (irq3-irq1); timer input and out- put signals (t in and t out ); (figure 13). comparator inputs. port 3, pins p31 and p32 each have a comparator front end. the comparator reference volt- age, pin p33, is common to both comparators. in analog mode, the p31 and p32 are the positive inputs to the com- parators and p33 is the reference voltage supplied to both comparators. in digital mode, pin p33 can be used as a p33 register input or irq1 source. table 3. port 3 pin assignments pin i/o ctc1 an in int. p0 hs p1 hs p2 hs ext p31 in t in an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 d/r p34 out r/d dm p35 out r/d p36 out t out r/d p37 out notes: hs = handshake signals d = dav r = rdy
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-25 1 figure 13. port 3 con?uration d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) from stop mode recovery source 1 = analog 0 = digital irq2, tin, p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an. port 3 (i/o or control) Z89135/136 mcu - + - +
Z89135/136 (romless) low-cost dtad controller zilog 1-26 p r e l i m i n a r y ds97tad0300 pin fuctions (continued) port 4. (p47-p40). port 4 is an 8-bit, bidirectional, cmos- compatible i/o port (figure 14). these eight i/o lines are configured under software control as an input or output, in- dependently. port 4 is always available for i/o operation. the input buffers are schmitt-triggered. bits programmed as outputs may be globally programmed as either push- pull or open-drain. port 4 is a bit programmable general-purpose i/o port. the control registers for port 4 are mapped into the expanded register file (bank f) of the z8. auto latch. the auto latch on port 4 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. figure 14. port 4 con?uraton oen out in pa d auto latch port 4 (i/o) Z89135/136 mcu r = 500 k w 1.5 2.3v hysteresis open-drain
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-27 1 port 5. (p57-p50). port 5 is an 8-bit, bidirectional, cmos- compatible i/o port (figure 15). these eight i/o lines are configured under software control as an input or output, in- dependently. port 5 is always available for i/o operation. the input buffers are schmitt-triggered. bits programmed as outputs may be globally programmed as either push- pull or open-drain. port 5 is a bit programmable general-purpose i/o port. the control registers for port 5 are mapped into the expanded register file (bank f) of the z8. auto latch. the auto latch on port 5 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. figure 15. port 5 con?uration oen out in pa d auto latch port 5 (i/o) Z89135/136 mcu r = 500 k w 1.5 2.3v hysteresis open-drain
Z89135/136 (romless) low-cost dtad controller zilog 1-28 p r e l i m i n a r y ds97tad0300 functional description the z8 ccp core incorporates special functions to en- hance the z8? application in industrial, scientific research and advanced technologies applications. reset. the device is reset in one of the following condi- tions: n power-on reset n watch-dog timer n stop-mode recovery source n external reset program memory. the z8 addresses up to 24 kb of inter- nal program memory and 40 kb external memory (figure 16). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that correspond to the five user interrupts and one dsp interrupt. byte 12 to byte 24575 consists of on-chip mask-programmed rom. at addresses 24576 and great- er, the z8 executes external program memory. in rom- less mode, the z8 will execute external program memory beginning at byte 12 and continuing through byte 65535. figure 16. program memory map 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom in rom mode location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 24575 external rom and ram 65535
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-29 1 rom protect . the 24 kb of internal program memory for the z8 is mask programmable. a rom protect feature pre- vents ?umping?of the rom contents of program memory by inhibiting execution of ldc, ldci, lde, and ldei in- structions. the rom protect option is mask-programma- ble, to be selected by the customer at the time when the rom code is submitted. data memory. (/dm). in rom mode, the z8 can address up to 40 kb of external data memory beginning at location 24576 (figure 17). in romless mode, the z8 can address the full 64 kb of external data memory beginning at loca- tion 12. external data memory may be included with, or separated from, the external program memory space. /dm, an optional i/o function that can be programmed to appear on port 34, is used to distinguish between data and program memory space. the state of the /dm signal is controlled by the type of instruction being executed. an ldc opcode references program (/dm inactive) mem- ory, and an lde instruction references data (/dm active low) memory. figure 17. data memory map external data memory not addressable (in rom mode) 65535 24756 0
Z89135/136 (romless) low-cost dtad controller zilog 1-30 p r e l i m i n a r y ds97tad0300 functional description (continued) register file. the standard z8 register file consists of four i/o port registers, 236 general-purpose registers, and 15 control and status registers (r3-r0, r239-r4, and r255- r241, respectively). the instructions access registers di- rectly or indirectly through an 8-bit address field. this al- lows a short, 4-bit register address using the register pointer (figure 18). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working register group (fig- ure 19). note: register group e (registers e0-ef) is only access- ed through a working register and indirect addressing modes. figure 18. register pointer register d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank working register group rp r253 default setting after reset = 00000000 figure 19. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group r7 r6 r5 r4 r253 r239 i/o ports specified working register group the upper nibble of the register file address provided by the instruction points to the specified working-register group r15 r3 r255 r240 r3 r2 r1 r0 group 15 (f) control registers group 14 (e) group 13 (d) group 4 (4) group 3 (3) group 2 (2) group 1 (1) group 0 (0) r223 r79 r63 r47 r31 r0
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-31 1 ram protect. the upper portion of the z8? ram address spaces 80fh to efh (excluding the control registers) are protected from reading and writing. the ram protect bit option is mask-programmable and is selected by the cus- tomer when the rom code is submitted. after the mask option is selected, the user activates from the internal rom code to turn off/on the ram protect by loading a bit d6 in the imr register to either a 0 or a 1, respectively. a 1 in d6 indicates ram protect enabled. stack. the z8? external data memory or the internal reg- ister file is used for the stack. the 16-bit stack pointer (r255-r254) is used for the external stack which can re- side only from 24576 to 65535 in rom mode or 0 to 65535 in romless mode. an 8-bit stack pointer (r255) is used for the internal stack that resides within the 236 general- purpose registers (r239-r4). sph can be used as a gen- eral-purpose register when using internal stack only. expanded register file. the register file on the z8 has been expanded to allow for additional system control reg- isters, and for mapping of additional peripheral devices along with i/o ports into the register address area. the z8 register address space has now been implemented as 16 banks of 16 registers groups per bank (figure 20). these register banks are known as the erf (expanded register file). bits 7-4 of register rp (register pointer) select the working register group. bits 3-0 of register rp select the expanded register bank (figure 20). the smr register, wdt register, control and data regis- ters for port 4 and port 5, and the dsp control register are located in bank f of the expanded register file. bank b of the expanded register file consists of the mailbox in- terface in which the z8 and the dsp communicate. the rest of the expanded register is not physically implement- ed and is open for future expansion.
Z89135/136 (romless) low-cost dtad controller zilog 1-32 p r e l i m i n a r y ds97tad0300 functional description (continued) figure 20. expanded register file architecture 7 654321 0 working register group pointer expanded register bank pointer ffh foh 7fh 0fh 00h z8 reg. file register pointer ffh feh fdh fch fbh fa h f9h f8h f7h f6h f5h % f4 f3h f2h f1h f0h spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr u u 0 u 0 0 u 0 0 1 u u u u 0 (f) 0fh (f) 0eh (f) 0dh (f) 0ch (f) 0bh (f) 0ah (f) 09h (f) 08h (f) 07h (f) 06h (f) 05h (f) 04h (f) 03h (f) 02h (f) 01h (f) 00h wdtmr smr u u 0 u u 0 u 1 0 1 u u u u 0 u u 0 u u 0 u 0 0 1 u u u u 0 u u 0 u u 0 u 0 0 1 u u u u 0 u u 0 u u 0 u 1 0 1 u u u u 0 u u 0 u u 0 u 1 0 1 u u u u 0 u u 0 u u 0 u 0 0 1 u u 0 u 0 u u 0 u u 0 u 1 0 1 0 u 0 u 0 uuu0 11 0 1 0010 00 0 0 register group 0 (0) z8 expanded register bank (f) reset condition z8 standard register bank (0) register group 15(f) z8 standard control registers reset condition u = unknown d7 d6 d5 d4 d3 d2 d1 d0 reserved will not be reset with a stop-mode recovery * * * * * reserved reserved reserved dsp con reserved reserved reserved reserved p45con p5m p5 p4m p4 reserved pcon register bank (0) uuu1uuuu uuu0uuu0 1111 11 1 1 uuuuuuuu 1111 11 1 1 uuuuuuuu 1111 11 1 0 0 1 2 3 4 5 6 7 8 9 a b c d e f z8 expanded register bank (b) z8-dsp mailbox interface reserved ? ? = for romless mode, reset condition 10110110 1111uuuu uuuuuuuu uuuuuuuu uuuuuuuu register group 0 reset condition (0) 03h p3 (0) 02h p2 (0) 01h p1 (0) 00h p0 * * * * (r0...r15)
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-33 1 figure 21. interrupt block diagram interrupt edge select irq register (d6, d7) irq1, 3, 4, 5 irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 irq2 table 4. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, p32, an2 0, 1 external (p32), programmable rise or fall edge triggered irq1 /dav1, p33 2, 3 external (p33), fall edge triggered irq2 /dav2, p31,t in , an2 4, 5 external (p31), programmable rise or fall edge triggered irq3 irq3 6, 7 internal (dsp activated), fall edge triggered irq4 t0 8, 9 internal irq5 ti 10, 11 internal
Z89135/136 (romless) low-cost dtad controller zilog 1-34 p r e l i m i n a r y ds97tad0300 functional description (continued) interrupts. the z8 has six different interrupts from six dif- ferent sources. the interrupts are maskable and prioritized (figure 21). the six sources are divided as follows; three sources are claimed by port 3 lines p33-p31, two in counter/timers, and one by the dsp (table 4). the inter- rupt mask register globally or individually enables or dis- ables the six interrupt requests.when more than one inter- rupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the interrupt priority register. an interrupt machine cycle is activated when an interrupt request is granted. this disables all subsequent interrupts, pushes the program counter and status flags to the stack, and then branches to the program memory vector location reserved for that interrupt. all z8 interrupts are vectored through locations in the pro- gram memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 may be rising, falling or both edge trig- gered, and are programmable by the user. the software may poll to identify the state of the pin. programming bits for the interrupt edge select is located in the irq register (r250), bits d7 and d6. the configu- ration is shown in table 5. clock. the Z89135/136 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 20.48 mhz max., with a series resistance (rs) less than or equal to 100 ohms. the system clock (sclk) is one half the crystal frequency. the crystal is connected across xtal1 and xtal2 using capacitors from each pin to ground. table 5. irq register irq interrupt edge d7 d6 p31 p32 00ff 01fr 10rf 1 1 r/f r/f notes: f = falling edge r = rising edge figure 22. oscillator con?uration xtal1 xtal2 c1 c2 c1 c2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal lc external clock l
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-35 1 counter/timers. there are two 8-bit programmable counter/timers (t0-t1), each driven by its own 6-bit pro- grammable prescaler. the t1 prescaler is driven by inter- nal or external clock sources; however, the t0 prescaler is driven by the internal clock only (figure 23). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when the counter reaches the end of the count, a timer interrupt re- quest, irq4 (t0) or irq5 (t1), is generated. the counters can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). the counters, but not the prescalers, are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and is either the internal mi- croprocessor clock divided by four, or an external signal in- put through port 31. the timer mode register configures the external timer input (p31) as an external clock, a trig- ger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. the counter/timers can be cascaded by connecting the t0 output to the input of t1. figure 23. counter/timer block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ? 16 ? 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register clock logic irq4 t p36 out irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock d0,d1 (smr) ? 4 ? 2 ? 2 ? 2 ? 2 osc t0, t2, t3 dsp clock d7, d6 (f) oc (dsp con)
Z89135/136 (romless) low-cost dtad controller zilog 1-36 p r e l i m i n a r y ds97tad0300 functional description (continued) port configuration register (pcon) . the pcon regis- ter configures the port individually; comparator output is on port 3. the pcon register is located in the expanded register file at bank f, location 00h (figure 24). comparator output port 3 (d0) . bit 0 controls the com- parator use in port 3. a 1 in this location brings the com- parator outputs to p34 and p35, and a 0 releases the port to its standard i/o configuration. port 4 and 5 configuration register (p45con) . the p45con register configures port 4 and port 5, individual- ly, to open-drain or push-pull active. this register is located in the expanded register file at bank f, location 06h (figure 25). port 4 open-drain (d0). port 4 can be configured as an open-drain by resetting this bit (d0 = 0) or configured as push-pull active by setting this bit (d0 = 1). the default val- ue is 1. port 5 open-drain (d4). port 5 can be configured as an open-drain by resetting this bit (d4 = 0) or configured as push-pull active by setting this bit (d4 = 1). the default val- ue is 1. figure 24. port con?uration register (pcon) d7 d6 d5 d4 d3 d2 d1 d0 pcon (f) %00 r always "1" w 0 p34,p37 standard output 1 p34,p37 comparator output r always "1" w no effect note: reset condition is 1 1111110 figure 25. port 4 and 5 con?uration register (f) 06h (write only) p45m (fh) 06h (write only) port 4 configuration bit 0 open-drain 1 push-pull no effect port 5 configuration bit 0 open-drain 1 push-pull no effect d7 d6 d5 d4 d3 d2 d1 d0
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-37 1 power-on rese t (por) . a timer circuit clocked by a ded- icated on-board rc oscillator is used for the power-on re- set (por) timer function. the por time allows v cc and the oscillator circuit to stabilize before instruction execu- tion begins. the por timer circuit is a one-shot timer triggered by one of three conditions: n power fail to power ok status n stop-mode recovery (if d5 of smr=1) n wdt time-out. the por time is a nominal 5 ms. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock, rc/lc oscillators). halt. halt turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external inter- rupts irq0, irq1, irq2, and irq3 remain active. the de- vices are recovered by interrupts, either externally or inter- nally generated. stop. this instruction turns off the internal clock and ex- ternal crystal oscillation. it reduces the standby current to 300 m a or less. the stop mode is terminated by a reset only, either by wdt time-out, por, smr recovery or ex- ternal reset. this causes the processor to restart the appli- cation program at address 000ch. in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user must execute a nop (opcode=ffh) immediately before the appropriate sleep instruction, for example: ff nop ;clear the pipeline 6f stop ;enter stop mode or ff nop ;clear the pipeline 7f halt ;enter halt mode
Z89135/136 (romless) low-cost dtad controller zilog 1-38 p r e l i m i n a r y ds97tad0300 functional description (continued) stop-mode recovery register (smr) . this register se- lects the clock divide value and determines the mode of stop-mode recovery (figure 26). all bits are write only, except bit 7 which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level is required from the recovery source. bit 5 con- trols the reset delay after recovery. bits 2, 3, and 4, or the smr register, specify the source of the stop-mode recov- ery signal. bits 0 and 1 determine the time-out period of the wdt. the smr is located in bank f of the expanded reg- ister group at address 0bh. figure 26. stop-mode recovery register (smr) d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0bh w 0 stop delay on* 1 stop delay off r always "1" w 0 low stop recovery level* 1 high stop recovery level r always "1" w no effect r 0 por* 1 stop-mode recovery * default setting after reset ? reset after stop-mode recovery w 000 por only* 001 no effect 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 r always "1" w 00 sclk/tclk not divide by 16? 01 sclk/tclk not divide by 16 10 sclk/tclk divide by 16 11 sclk/tclk divide by 16 r always "1"
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-39 1 sclk/tclk divide-by-16 select (d0) . d0 of the smr controls a divide-by-16 prescaler of sclk/tclk. the pur- pose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). stop-mode recovery source (d4-d2) . these three bits of the smr specify the wake-up source of the stop-mode recovery (figure 27 and table 6). stop-mode recovery delay select (d5). this bit, if high, disables the 5 ms /reset delay after stop-mode recov- ery. the default configuration of this bit is one. if the ?ast wake-up is selected, the stop-mode recovery source is kept active for at least 5 tpc. stop-mode recovery edge select (d6). a 1 in this bit po- sition indicates that a high level on any one of the recovery sources wakes the z89165 from stop mode. a 0 indi- cates low level recovery. the default is 0 on por . cold or warm start (d7). this bit is set by the device upon entering stop mode. it is active high, and is 0 (cold) on por/wdt /reset. this bit is read only. it is used to distinguish between cold or warm start. figure 27. stop-mode recovery source p31 p32 p33 p27 stop-mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) to p33 data latch and irq1 to por reset smr d4 d3 d2 0 0 0 vdd smr smr smr smr smr d4 d3 d2 0 1 0 0 1 1 d4 d3 d2 1 0 0 d4 d3 d2 1 0 1 d4 d3 d2 1 1 0 d4 d3 d2 1 1 1 p20 p23 p20 p27 mux table 6. stop-mode recovery source smr:432 operation description of action d4 d3 d2 0 0 0 por and/or external reset recovery 0 0 1 no effect 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27
Z89135/136 (romless) low-cost dtad controller zilog 1-40 p r e l i m i n a r y ds97tad0300 functional description (continued) dsp control register (dspcon). the dspcon register controls various aspects of the z8 and the dsp. it can con- figure the internal system clock (sclk) or the z8, reset, and halt of the dsp, and control the interrupt interface between the z8 and the dsp (table 7). z8 irq3 (d0). this bit, when read, indicates the status of z8 irq3. z8 irq3 is set by the dsp by writing to d9 of dsp external register 4 (icr). by writing a 1 to this bit, z8 irq3 is reset. dsp int2 (d1). this bit is linked to dsp int2. writing a 1 to this bit sets dsp int2. reading this bit indicates the sta- tus of dsp int2. dsp run (d4). this bit defines the halt mode of the dsp. if this bit is set to 0, then the dsp clock is turned off to minimize power consumption. after this bit is set to 1, then the dsp will continue code execution from where it was halted. after a hardware reset, this bit is reset to 1. dsp reset (d5). setting this bit to 1 will reset the dsp. if the dsp was in halt mode, this bit is automatically pre- set to 1. writing a 0 has no effect. z8 sclk (d8-d7). these bits define the sclk frequency of the z8. the oscillator can be divided by 8, 4, or 2. after a reset, both of these bits are defaulted to 00. table 7. dsp control register (f) 0ch [read/write] field dspcon (f)0ch position attrib value label z8_sclk 76------ r/w 00 01 1x 2.5 mhz (osc/8) 5 mhz (osc/4) 10 mhz (osc/2) dsp_reset --5----- r w0 1 return ? no effect reset dsp dsp_run ---4---- r/w 0 1 halt_dsp run_dsp reserved ----32-- w r no effect return ? no effect intfeedback ------1- r w1 0 fb_dsp_int2 set dsp_int2 no effect intfeedback -------0 r w1 0 fb_z8_irq3 clear irq3 no effect
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-41 1 watch-dog timer mode register (wdtmr ). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction and refreshed on subse- quent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the por clock source is selected with bit 4 of the wdt register (figure 28). the wdtmr is accessable only within 64 z8 clock cyles after por. figure 28. watch-dog timer mode register d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (fh) 0fh wdt tap int rc osc external clock 00 5 ms 256 tpc 01 15 ms 512 tpc 10 25 ms 1024 tpc 11 100 ms 4096 tpc wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal * default setting after reset * * * * w no effect r alway "1"
Z89135/136 (romless) low-cost dtad controller zilog 1-42 p r e l i m i n a r y ds97tad0300 wdt time select (d0,d1) . selects the wdt time period. it is configured as shown in table 8. wdt during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. the default is 1. wdt during stop (d3). this bit determines whether or not the wdt is active during stop mode. since xtal clock is stopped during stop mode, the on-board rc has to be selected as the clock source to the por counter. a 1 indicates active during stop. the default is 1. clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscil- lator is bypassed and the por and wdt clock source is driven from the external pin, xtal1. the default configu- ration of this bit is 0 which selects the rc oscillator . table 8. wdt time select time-out of time-out of d1 d0 internal rc osc xtal clock 0 0 5 ms min 256 tpc 0 1 15 ms min 512 tpc 1 0 25 ms min 1024 tpc 1 1 100 ms min 4096 tpc notes: tpc = xtal clock cycle the default on reset is 15 ms. figure 29. resets and wdt clk 18 clock reset generator reset clear wdt tap select rc osc. ck clr 5 ms por 5 ms 15 ms 25 ms 100 ms 2v operating voltage det. internal reset wdt select (wdtmr) ck source select (wdtmr) xtal vdd 2v ref. from stop mode recovery source wdt stop delay select (smr) 12 ns glitch filter + - 4 clock filter wdt/por counter chain m u x /reset
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-43 1 dsp registers description general. the dsp is a high-performance second genera- tion cmos digital signal processor with a modified har- vard-type architecture with separate program and data ports. the design has been optimized for processing pow- er and saving silicon space. registers. the dsp has eight internal registers and sev- en external registers. the external registers are for the a/d and d/a converters, and the mailbox and interrupt interfac- ing between dsp to the z8. external registers are access- ed in one machine cycle, the same as internal registers. dsp registers there are 15 internal and extended 16-bit registers which are defined in table 9. ext3-ext0 . (external registers 3-0) are the mailbox registers in which the dsp and the z8 communicate. these four 16 bit registers correspond to the eight outgo- ing and eight incoming 8-bit registers in bank b of the z8? expanded register file. ext4. (dsp interrupt control register (icr)) controls the interrupts in the dsp as well as the interrupts in common between the dsp and the z8. it is accessible by the dsp only, except for the bit f and bit 9. ext5. (d/a and a/d data register) is used by both d/a and a/d converters. the d/a converter will be loaded by writing to this register, while the a/d converter will be ad- dressed by reading from this register. the register ext5 is accessible by the dsp only. ext6. (analog control register) controls the d/a and a/d converters. it is a read/write register accessible by the dsp only. table 9. dsp registers register attribute register de?ition bus read data-bus x read/write x multiplier input, 16-bit y read/write y multiplier input, 16-bit a read/write accumulator, 24-bit sr read/write status register sp read/write stack pointer pc read/write program counter p read output of mac, 24-bit ext0 read write z8 erf bank b, register 00-01 (from z8) z8 erf bank b, register 08-09 (to z8) ext1 read write z8 erf bank b, register 02-03 (from z8) z8 erf bank b, register 0a-0b (to z8) ext2 read write z8 erf bank b, register 04-05 (from z8) z8 erf bank b, register 0c-0d (to z8) ext3 read write z8 erf bank b, register 06-07 (from z8) z8 erf bank b, register 0e-0f (to z8) ext4 read/write dsp interrupt control register ext5 read write a/d converter d/a converter ext6 read/write analog control register
Z89135/136 (romless) low-cost dtad controller zilog 1-44 p r e l i m i n a r y ds97tad0300 dsp-z8 mailbox to receive information from the dsp, the z8 uses eight in- coming registers which are mapped in the z8 extended register file (bank b, 08 to 0f). the dsp treats these as four 16-bit registers that correspond to the eight incoming z8 registers (figure 30). both the outgoing registers and the incoming registers share the same dsp address (ext3-ext0). the z8 can supply the dsp with data through eight outgo- ing registers mapped into both the z8 expanded register file (bank b, registers 00 to 07) and the external register interface of the dsp. these registers are read/write and can be used as general-purpose registers of the z8. the dsp can only read information from these registers. since the dsp uses a 16-bit data format and the z8 an 8-bit data format, eight outgoing registers of the z8 correspond to four dsp registers. the dsp can only read information from the outgoing registers. note: the z8 can read and write to erf bank b r00-r07, registers 08-0f are read only from the z8. figure 30. z8-dsp interface outgoing registers incoming registers dsp interrupt control register d/a and a/d data registers analog control register (b)00, (b)01 (b)02, (b)03 (b)04, (b)05 (b)06, (b)07 (b)08, (b)09 (b)0a, (b)0b (b)0c, (b)0d (b)0e, (b)0f (f)0c ext0 ext2 ext0 ext2 ext4 ext1 ext3 ext1 ext3 ext5 ext6 d7, d1 z8 data bus dsp data bus d9 d2
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-45 1 . table 10. z8 outgoing registers (read only from dsp) field position attrib value label outgoing [0] (b)00 76543210 r/w %nn (b)00/dsp_ext0_hi outgoing [1] (b)01 76543210 r/w %nn (b)01/dsp_ext0_lo outgoing [2] (b)02 76543210 r/w %nn (b)02/dsp_ext1_hi outgoing [3] (b)03 76543210 r/w %nn (b)03/dsp_ext1_lo outgoing [4] (b)04 76543210 r/w %nn (b)04/dsp_ext2_hi outgoing [5] (b)05 76543210 r/w %nn (b)05/dsp_ext2_lo outgoing [6] (b)06 76543210 r/w %nn (b)06/dsp_ext3_hi outgoing [7] (b)07 76543210 r/w %nn (b)07/dsp_ext3_lo table 11. z8 incoming registers (write only from dsp field position attrib value label incoming [8] (b)08 76543210 r %nn dsp_ext0_hi w no effect incoming [9] (b)09 76543210 r %nn dsp_ext0_lo w no effect incoming [a] (b)0a 76543210 r %nn dsp_ext1_hi w no effect incoming [b] (b)0b 76543210 r %nn dsp_ext1_lo w no effect incoming [c] (b)0c 76543210 r %nn dsp_ext2_hi w no effect incoming [d] (b)0d 76543210 r %nn dsp_ext2_lo w no effect incoming [e] (b)0e 76543210 r %nn dsp_ext3_hi w no effect incoming [f] (b)0f 76543210 r %nn dsp_ext3_lo w no effect table 12. dsp mailbox registers field position attrib value label dsp_ext0 fedcba9876543210 r %nnnn (b)00, (b)01 mail box w (b)08, (b)09 dsp_ext1 fedcba9876543210 r %nnnn (b)02, (b)03 mail box w (b)0a, (b)0b dsp_ext2 fedcba9876543210 r %nnnn (b)04, (b)05 mail box w (b)0c, (b)0d dsp_ext3 fedcba9876543210 r %nnnn (b)06, (b)07 mail box w (b)0e, (b)0f
Z89135/136 (romless) low-cost dtad controller zilog 1-46 p r e l i m i n a r y ds97tad0300 dsp interrupts the dsp processor has three interrupt sources (int2, int1, int0) (figure 31). these sources have different pri- ority levels (figure 32). the highest priority, the next lower and the lowest priority level are assigned to int2, int1 and int0, respectively. the dsp does not allow interrupt nesting (interrupting service routines that are currently be- ing executed). when two interrupt requests occur simulta- neously the dsp starts servicing the interrupt with the highest priority level. figure 33 shows the interprocessor interrupts mechanism. figure 31. dsp interrupts interrupt priority logic interrupt request logic interrupt mask logic feedback z8_int mpx z8_int a/d int d/a int ipr2 ipr1 ipr0 fb dsp clear_int1 clear_int2 clear_int0 enable_int int2 int1 int0 int2 int1 int0 figure 32. dsp interrupt priority structure int0 int1 int2 dsp execution int2 int0 int1 int2 figure 33. interprocessor interrupts structure 4 9 after serving irq3, set d0 to clear the interrupt request. the dsp sets d9 to interrupt z8 via z8 irq3. irq3 of the z8 dsp int2 after serving int2, set d4 to clear the interrupt request. on the z8, set d1 to interrupt dsp via dsp int2. dsp side z8 side 10 dsp con icr (ext4)
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-47 1 interrupt control register (icr) . the icr is mapped into ext4 of the dsp (table 13). the bits are defined as fol- lows: dsp_irq2 (z8 interrupt). this bit can be read by both z8 and dsp and can be set only by writing to the z8 expand- ed register file (bank f, roc, bit 0). this bit asserts irq2 of the dsp and can be cleared by writing to the clear_irq2 bit. dsp_irq1 (a/d interrupt). this bit can be read by the dsp only and is set when valid data is present at the a/d output register (conversion done). this bit asserts irq1 of the dsp and can be cleared by writing to the clear_irq1bit. dsp_irq0 (d/a interrupt). this bit can be read by dsp only and is set by timer3. this bit assists irq0 of the dsp and can be cleared by writing to the clear_irq0 bit. dsp_maskintx. these bits can be accessed by the dsp only. writing a 1 to these locations allows the int to be serviced, while writing a 0 masks the corresponding int off. table 13. ext4 dsp interrupt control register (icr) de?ition field position attrib value label dsp_irq2 f--------------- r 1 set_irq2 0 reset_irq2 f--------------- w no effect dsp_irq1 -e-------------- r 1 set_irq1 0 reset_irq1 -e-------------- w no effect dsp_irq0 --d------------- r 1 set_irq0 0 reset_irq0 --d------------- w no effect dsp_maskint2 ---c------------ r/w 1 enable_int2 0 disable_int2 dsp_maskint1 ----b----------- r/w 1 enable_int1 0 disable_int1 dsp_maskint0 -----a---------- r/w 1 enable_int0 0 disable_int0 z8_irq3 ------9--------- r return "0" ------9--------- w 1 set_z8_irq3 0 reset_z8_irq3 dspintenable -------8-------- r/w 1 enable 0 disable dsp_ipr2 --------7------- r/w binary ipr2 dsp_ipr1 ---------6------ r/w binary ipr1 dsp_ipr0 ----------5----- r/w binary ipr0 clear_irq2 -----------4---- r return "0" -----------4---- w 1 clear_irq2 0 has_no_effect clear_irq1 ------------3--- r return "0" ------------3--- w 1 clear_irq1 0 no effect clear_irq0 -------------2-- r return "0" -------------2-- w 1 clear_irq0 0 no effect reserved --------------10 w no effect "0" r
Z89135/136 (romless) low-cost dtad controller zilog 1-48 p r e l i m i n a r y ds97tad0300 z8_irq3. this bit can be read from both z8 and dsp and can be set by dsp only. addressing this location accesses bit d3 of the z8 irq register, hence this bit is not imple- mented in the icr. during the interrupt service routine ex- ecuted on the z8 side, the user has to reset the z8_irq3 bit by writing a 1 to bit d0 of the dspcon. the hardware of the z89165/c66 automatically resets z8_irq3 bit three instructions of the z8 after 1 is written to its location in reg- ister bank 0f. this delay provides the timing synchroniza- tion between the z8 and the dsp sides during interrupts. in summary, the interrupt service routine of the z8 for irq3 should be finished by: dsp enable_int. writing a 1 to this location enables glo- bal interrupts of the dsp while writing 0 disables them. a system reset globally disables all interrupts. dsp_iprx. this three-bit group defines the interrupt se- lection logic according to table 14. clear_irqx. these bits can be accessed by the dsp only. writing a 1 to these locations rests the corresponding dsp_irqx bits to 0. clear_irqx are virtual bits and are not implemented. dsp analog data registers the d/a conversion is dsp driven by sending 10-bit data to the ext5 of the dsp. the six remaining bits of ext5 are not used (figure 34). a/d supplies 8-bit data to the dsp through the register ext5 of the dsp. from the 16 bits of ext5, only bits 2 through 9 are used by the a/d (figure 35). bits 0 and 1 are padded with zeroes ld ;rp,#%0f or ;r12,#%01 pop ;rp iret ; table 14. dsp interrupt selection dsp_ipr[2-0] 2 1 0 z8_int is switched to a/d_int is switched to d/a_int is switched to 0 0 0 int2 int1 int0 0 0 1 int1 int2 int0 0 1 0 int2 int0 int1 0 1 1 int1 int0 int2 1 0 0 int0 int2 int1 1 0 1 int0 int1 int2 1 1 0 reserved reserved reserved 1 1 1 reserved reserved reserved figure 34. ext5 regoster d/a mode de?ition fedcba9 87 65432 10 10-bit data for d/a (write only) reserved figure 35. ext5 register a/d mode de?ition fedcba9876543210 reserved 8-bit data from a/d converter (read only) reserved
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-49 1 analog control register (acr) the analog control register is mapped to register ext6 of the dsp (table 15). this read/write register is accessible by the dsp only. the 16-bit field of ext6 defines modes of both the a/d and the d/a. the high byte configures the d/a, while the low byte controls the a/d mode. table 15. ext6 analog control register (acr) field position attrib value label mpx_dsp_int0 f--------------- r/w 1 0 p26 timer3 reserved -edcb----------- r w return ? no effect d/a_samplingrate -----a98-------- r/w 11x 101 100 010 011 001 000 reserved reserved 64 khz 16 khz 10 khz 4 khz reserved dsp_port --------76------ r/w user de?ed dsp outputs enable a/d ----------5----- r/w 1 0 a/d enabled a/d disabled conversiondone -----------4---- w r1 0 no effect done not done startconversion ------------3--- r/w 1 0 start wait timer a/d_samplingrate -------------210 r/w 11x 101 100 010 011 001 000 reserved reserved 128 khz 64 khz 32 khz 16 khz 8 khz
Z89135/136 (romless) low-cost dtad controller zilog 1-50 p r e l i m i n a r y ds97tad0300 dsp irq0. this bit defines the source of dsp irq0 inter- rupt. d/a_sampling rate. this field defines the sampling rate of the d/a output. it changes the period to timer3 interrupt and the maximum possible accuracy of the d/a (table 16). dsp0. dsp0 is a general-purpose output pin connected to bit 6. this bit has no special significance and may be used to output data by writing to bit 6. dsp1. dsp1 is a general-purpose output pin connected to bit 7. this bit has no special significance and may be used to output data by writing to bit 7. enable a/d. writing a 0 to this location disables the a/d converter, a 1 will enable it. a hardware reset forces this bit to be 0. conversion done. this read only flag indicates that the a/d conversion is complete. upon reading ext5 (a/d da- ta), the conversion done flag is cleared. start a/d conversion. writing a 1 to this location immedi- ately starts one conversion cycle. if this bit is reset to 0 the input data is converted upon successive timer2 time-outs. a hardware reset forces this bit to be 1. a/d_sampling rate. this field defines the sampling rate of the a/d. it changes the period of timer2 interrupt (table 17). dsp timers timer2 is a free running counter that divides the xtal fre- quency (20.48 mhz) to support different sampling rates for the a/d converter. the sampling rate is defined by the an- alog control register. upon reaching the end of a count, the timer generates an interrupt request to the dsp. analogous to timer2, timer3 generates the different sam- pling rates for the d/a converter. timer3 also generates an interrupt request to the dsp upon reaching its final count value (figure 36). table 16. d/a data accuracy d/a_sampling rate d/a accuracy sampling rate 1 0 0 64 khz 8 bits 0 1 0 16 khz 10 bits 0 1 1 10 khz 10 bits 0 0 1 4 khz 10 bits table 17. a/d sampling rate a/d_sampling rate adc sampling rate 1 0 0 128 khz 0 1 1 64 khz 0 1 0 32 khz 0 0 1 16 khz 0 0 0 8 khz figure 36. timer2 and timer3 osc 20.48 mhz timer2 128, 64, 32, 16, 8 khz timer3 64, 16, 10, 4 khz a/d d/a
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-51 1 pulse width modulator (pwm) the pwm supports four different sampling rates (4, 10, 16, and 64 khz), according to the settings of bit 8, 9, 10 of the acr. the output of pwm can be assigned to logic 1 only during the active region (which is 4/5 of the output signal period). the output will be at logic 0 for the rest of the time. an exception occurs in 10 khz pwm, where the active re- gion covers the whole output signal period (figure 37). the active region is divided into 1024 time slots. in each of these time slots, the output can be set to logic 1 or logic 0. in order to increase the effective sampling rate, the pwm employs a special technique of distributing the ?ogic 1?pe- riod over the active region. the 10-bit pwm data is divided into two parts: the upper 5 bits (high_val) and the lower 5 bits (low_val). the 1024 time slots in the active region are divided into 32 equal groups, with 32 time slots in each group. the first slot of each of the 32 groups represents low_val, while high_val is represented by the remaining 31 time slots in each group. for example, a value of %13a is loaded into pwm data register ext 5: %13a = 01 0011 1010b = 314 high_val = 01001b = 9 low_val = 11010b = 26 26 out of 32 groups will then have their first slots set to log- ic 1. the remaining slots in each group have 9 time slots set to logic 1. for 10 khz pwm, the effective output frequency is 10k x 32 = 320 khz. figure 38 illustrates the waveform by using a 6-bit pwm data (3-bit high_val and 3-bit low_val). figure 37. pwm waveform (shaded area shows the active region) 4 khz 10 khz 16 khz 64 khz 250 m s 100 m s 62.5 m s 16 m s figure 38. pwm waveform of the active region (for a 6-bit pwm data) 4 khz 10 khz 16 khz 64 khz 250 m s 100 m s 62.5 m s 16 m s
Z89135/136 (romless) low-cost dtad controller zilog 1-52 p r e l i m i n a r y ds97tad0300 a/d converter (adc) analog to digital converter the a/d converter is an 8-bit half flash converter which uses two reference resistor ladders for its upper four bits (msbs) and lower four bits (lsbs) conversion. two refer- ence voltage pins, v ref+ (high) and v ref- (low), are pro- vided for external reference voltage supplies. during the sampling period, the converter is auto-zeroed before start- ing the conversion time depending on the external clock frequency and the selection of the a/d sampling rate. the sampling rates are in the order of 8, 10, 16, 64, or 128 khz (xtal = 20.48 mhz) in order to provide oversampling. the rates are software controlled by the acr (dsp external register 6). timer2 supports the adc. the maximum con- version time is 2 m s. conversion begins by writing to the appropriate bit in the analog control register (acr). the start commands are implemented in such a way as to begin a conversion at any time. if a conversion is in progress and a new start com- mand is received, then the conversion in progress is abort- ed and a new conversion initiated. this allows the pro- grammed values to be changed without affecting a conversion in progress. the new values take effect only af- ter a new start command is received. the adc can be disabled (for low power) or enabled by an analog control register bit. though the adc functions for a smaller input voltage and voltage reference, the noise and offsets remain constant over the specified electrical range. the errors of the con- verter will increase and the conversion time may also take slightly longer due to smaller input signals. figure 39. a/d converter 4-bit flash an in sample auto zero m 4-bit dac + 4 msb 4-bit flash auto zero 4 lsb latch 4 msb latch 4 lsb bits 9-2 register 12 of dsp
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-53 1 z8 expanded register file registers expanded register bank b figure 40. outgoing register to dsp ext0 (high byte) (b) 00h [read/write] figure 41. outgoing register to dsp ext0 (low byte) (b) 01h [read/write] figure 42. outgoing register to dsp ext1 (high byte) (b) 02h [read/write] figure 43. outgoing register to dsp ext1 (low byte) (b) 03h [read/write] 765 4321 0 dsp ext0, bits d15-d8 (b) 00 7654 3210 dsp ext0, bits d7-d0 (b) 01 765 4321 0 dsp ext1, bits d15-d8 (b) 02 765 4321 0 dsp ext1, bits d7-d0 (b) 03 figure 44. outgoing register to dsp ext2 (high byte) (b) 04h [read/write] figure 45. outgoing register to dsp ext2 (low byte) (b) 05h [read/write] figure 46. outgoing register to dsp ext3 (high byte) (b) 06h [read/write] figure 47. outgoing register to dsp ext3 (low byte) (b) 07h [read/write] 765 4321 0 dsp ext2, bits d15-d8 (b) 04 7654 3210 dsp ext2, bits d7-d0 (b) 05 7654 3210 dsp ext3, bits d15-d8 (b) 06 765 4321 0 dsp ext3, bits d7-d0 (b) 07
Z89135/136 (romless) low-cost dtad controller zilog 1-54 p r e l i m i n a r y ds97tad0300 z8 expanded register file registers (continued) figure 48. incoming register to dsp ext0 (high byte) (b) 08h [read/write] figure 49. incoming register to dsp ext0 (low byte) (b) 09h [read/write] figure 50. incoming register to dsp ext1 (high byte) (b) 0ah [read/write] figure 51. incoming register to dsp ext1 (low byte) (b) 0bh [read/write] 7654 3210 dsp ext0, bits d15-d8 (b) 08 7654 3210 dsp ext0, bits d7-d0 (b) 09 765 4321 0 dsp ext1, bits d15-d8 (b) 0a 7654 3210 dsp ext1, bits d7-d0 (b) 0b figure 52. incoming register to dsp ext2 (high byte) (b) 0ch [read/write] figure 53. incoming register to dsp ext2 (low byte) (b) 0dh [read/write] figure 54. incoming register to dsp ext3 (high byte) (b) 0eh [read/write] figure 55. incoming register to dsp ext3 (low byte) (b) 0fh [read/write] 765 4321 0 dsp ext2, bits d15-d8 (b) 0c 7654 3210 dsp ext2, bits d7-d0 (b) 0d 765 4321 0 dsp ext3, bits d15-d8 (b) 0e 765 4321 0 dsp ext3, bits d7-d0 (b) 0f
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-55 1 expanded register bank f figure 56. port con?uration register (pcon) (f) 00h [write only] figure 57. port 4 data register (f) 02h [write only] figure 58. port 4 mode register (f) 03h [write only] figure 59. port 5 data register (pcon) (f) 04h [read/write] d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h r always "1" w 0 p34,p37 standard output 1 p34,p37 comparator output r always "1" w no effect note: reset condition is 1 1111110 d7 d6 d5 d4 d3 d2 d1 d0 data p4d (fh) 02h d7 d6 d5 d4 d3 d2 d1 d0 p40-p47 i/o definition 0 defines bit as output 1 defines bit as input returns "ff" u p on read p4m (fh) 03h d7 d6 d5 d4 d3 d2 d1 d0 data p5d (fh) 04h figure 60. port 5 mode register (pcon) (f) 05h [write only] figure 61. port 4 and 5 con?uration register (f) 06h [write only] figure 62. stop-mode recovery register (f) 07h [read/write] d7 d6 d5 d4 d3 d2 d1 d0 p5m (fh) 05h p50-p57 i/o definition 0 defines bit as output 1 defines bit as input* returns "ff" upon read * default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 p45con (fh) 06h port 4 configuration bit 0 open drain * 1 push-pull active reserved port 5 configuration bit 0 open drain * 1 push-pull active reserved * default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0bh w 0 stop delay on* 1 stop delay off r always "1" w 0 low stop recovery level* 1 high stop recovery level r always "1" w no effect r 0 por* 1 stop-mode recovery * default setting after reset ? reset after stop-mode recovery w 000 por only* 001 no effect 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 r always "1" w 00 sclk/tclk not divide by 16? 01 sclk/tclk not divide by 16 10 sclk/tclk divide by 16 11 sclk/tclk divide by 16 r always "1"
Z89135/136 (romless) low-cost dtad controller zilog 1-56 p r e l i m i n a r y ds97tad0300 table 18. dsp control register (f) 0fh [read/write] field dspcon (f)0ch position attrib value label z8_sclk 76------ r/w 00 0.1 1x 2.5 mhz (osc/8) 5 mhz (osc/4) 10 mhz (osc/2) dsp_reset --5----- r w0 1 return ? no effect reset dsp dsp_run ---4---- r/w 0 1 halt_dsp run_dsp reserved ----32-- xx return ? no effect intfeedback ------1- r w1 0 fb_dsp_int2 set dsp_int2 no effect -------0 r w1 0 fb_z8_irq3 clear irq 3 no effect figure 63. watch-dog timer mode register (f) 0fh [read/write] d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (fh) 0fh wdt tap int rc osc external clock 00 5 ms 256 tpc 01 15 ms 512 tpc 10 25 ms 1024 tpc 11 100 ms 4096 tpc wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved * default setting after reset note : the wdtmr register is only accessed within 64 z8 ? clock cycles after por. * * * *
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-57 1 z8 control registers figure 64. reserved (f0h) figure 65. timer mode register (f1h: read/write) figure 66. counter/timer 1 register (f2h: read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count tin modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) tout modes 00 not used 01 t0 out 10 t1 out 11 internal clock out (p36) r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 t1 low byte initial value (when written) t1 low byte current value (when read) r242 t1 figure 67. prescaler 1 register (f3h: write only) figure 68. counter/timer 0 register (f4h: read/write) figure 69. prescaler 0 register (f5h: write only) d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1internal 0 t1external timing input (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 t0 low byte initial value (when written) t0 low byte current value (when read) r244 t0 0 t0 single pass 1 t0 modulo n d7 d6 d5 d4 d3 d2 d1 d0 count mode reserved prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0
Z89135/136 (romless) low-cost dtad controller zilog 1-58 p r e l i m i n a r y ds97tad0300 z8 control registers (continued) figure 70. port 2 mode register (f6h: write only) figure 71. port 3 mode register (f7h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p20 - p27 i/o definition 0 defines bit as output 1 defines bit as input * r246 p2m * default setting after reset * default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 pull-ups open drain * 1 port 2 pull-ups active 0 p31, p32 digital mode * 1 p31, p32 analog mode 0 p32 = input * p35 = output * 1 p32 = /dav0/rdy0 p35 = rdy0//dav0 00 p33 = input * p34 = output * 01 p33 = input p34 = /dm 10 p33 = input p34 = /dm 11 p33 = /dav1/rdy1 p34 = rdy1//dav1 0 p31 = input (tin) * p36 = output (tout) * 1 p31 = /dav2/rdy2 p36 = rdy2//dav2 0 p30 = input p37 = output reserved figure 72. port 0 mode register (f8h: write only) figure 73. interrupt priority register (f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p00 - p03 mode 00 output 01 input * 1x a11 - a8 stack selection 0 external 1 internal * p10 - p17 mode 00 byte output 01 byte input * 10 ad7 - ad0 11 high-impedance ad7 - ad0, /as, /ds, /r//w, a11 - a8, a15 - a12, if selected p04 - p07 mode 00 output 01 input * 1x a15 - a12 external memory timing 0 normal * 1 extended * default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved r249 ipr
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-59 1 figure 74. interrupt request register figure 75. interrupt mask register (fbh: read/write) figure 76. flag register (fch: read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq inter edge p31 p32 = 00 p31 p32 - = 01 p31 - p32 = 10 p31 - p32 - = 11 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = dsp irq4 = t0 irq5 = t1 d7 d6 d5 d4 d3 d2 d1 d0 1 enables ram protect 1 enables irq0-irq5 (d0 = irq0) 1 enables interrupts r251 imr d7 d6 d5 d4 d3 d2 d1 d0 r252 flags user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag figure 77. register pointer (fdh: read/write) figure 78. stack pointer high (feh: read/write) figure 79. stack pointer low (ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register file bank working register group d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp8 - sp15) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0 - sp7) r255 spl
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-60 1 package information figure 80. 68-pin plcc package diagram
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-61 1 ordering information speed 20 = 20.48 mhz package v = plastic leaded chip carrier (plcc) temperature s = 0 c to +55 c environmental c = plastic standard Z89135 z89136 20 mhz 20 mhz 68-pin plcc 68-pin plcc Z8913520vsc z8913620vsc example: z 89135 20 v s c environmental flow temperature package speed product number zilog prefix is a Z89135, 20.48 mhz, plcc, 0 c to +55 c, plastic standard flow
Z89135/136 (romless) low-cost dtad controller zilog 1-62 p r e l i m i n a r y ds97tad0300
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-63 1
Z89135/136 (romless) low-cost dtad controller zilog 1-64 p r e l i m i n a r y ds97tad0300
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-65 1
Z89135/136 (romless) zilog low-cost dtad controller ds97tad0300 p r e l i m i n a r y 1-66 1

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